It is desirable to improve the insulative characteristics of a semiconductor device.
According to one embodiment, a semiconductor device includes a first electrode, a semiconductor layer, and a first insulating portion. The first electrode extends along a first direction and includes a first electrode region and a second electrode region. A direction connecting the first electrode region and the second electrode region is along the first direction. The semiconductor layer includes first to third semiconductor regions, and third and fourth partial regions. The first semiconductor region includes a first partial region and a second partial region and is of a first conductivity type. The first partial region is separated from the first electrode region in a second direction crossing the first direction. A direction connecting the first partial region and the second partial region is aligned with a third direction crossing the first direction and the second direction. The second semiconductor region is separated from the second partial region in the second direction, and is of the first conductivity type. The third semiconductor region is provided between the second partial region and the second semiconductor region in the second direction, and is of a second conductivity type. The third partial region is separated from the second electrode region in the second direction. A direction connecting the first partial region and the third partial region is along the first direction. The fourth partial region is separated from the second electrode region in the third direction. The first insulating portion is provided between the first electrode region and the first partial region in the second direction, between the first electrode region and a portion of the second partial region in the third direction, between the first electrode region and the third semiconductor region in the third direction, between the first electrode region and the second semiconductor region in the third direction, between the second electrode region and the third partial region in the second direction, and between the second electrode region and the fourth partial region in the third direction. The first insulating portion has a first width and a second width. The first width is a length along the third direction between the first electrode region and the second semiconductor region. The second width is a length along the third direction between the second electrode region and the fourth partial region. The second width is wider than the first width.
According to another embodiment, a method for manufacturing a semiconductor device is disclosed. The method can include forming a first trench in a semiconductor member. The first trench extends in a first direction. The first trench includes a first trench region, a second trench region, and a third trench region. A direction connecting the first trench region and the second trench region is aligned with the first direction. The third trench region is between the first trench region and the second trench region. The first trench has a trench depth along a second direction crossing the first direction. The trench depth includes a first depth in the first trench region, a second depth in the second trench region, and a third depth in the third trench region. The second depth is shallower than the first depth. The third depth is between the first depth and the second depth. The trench depth decreases along a direction from the third trench region toward the second trench region. An opening of the first trench has an opening width along a third direction crossing the first direction and the second direction. The opening width includes a first opening width in the first trench region, a second opening width in the second trench region, and a third opening width in the third trench region. The second opening width is wider than the first opening width. The third opening width is between the first opening width and the second opening width. The opening width increases along the direction from the third trench region toward the second trench region. The method can include forming a first insulating film on a surface of the first trench, and forming a conductive layer in a space remaining in the first trench after the forming of the first insulating film and on another region of the semiconductor member where the first trench is not formed. The conductive layer includes a first conductive region on the first trench region, a second conductive region on the second trench region, and a third conductive region on the third trench region. The method can include performing etch-back of the conductive layer using a mask covering a portion of the second conductive region and a portion of the third conductive region to cause an upper surface of the first conductive region to be lower than an upper surface of the other region of the semiconductor member, cause at least a portion of the portion of the second conductive region and at least a portion of the first insulating film to be separated from each other in the third direction, cause at least a portion of the portion of the third conductive region and at least a portion of the first insulating film to be separated from each other in the third direction, cause a second distance along the third direction between the portion of the second conductive region and a second side surface of the semiconductor member in the second trench region to be longer than a first distance along the third direction between the first conductive region and a first side surface of the semiconductor member in the first trench region, and cause a third distance along the third direction between the portion of the third conductive region and a third side surface of the semiconductor member in the third trench region to be between the first distance and the second distance. In addition, the method can include forming a second insulating film in a space between the second side surface and the portion of the second conductive region and in a space between the third side surface and the portion of the third conductive region.
Various embodiments will be described hereinafter with reference to the accompanying drawings.
The drawings are schematic and conceptual; and the relationships between the thickness and width of portions, the proportions of sizes among portions, etc., are not necessarily the same as the actual values thereof. Further, the dimensions and proportions may be illustrated differently among drawings, even for identical portions.
In the specification and drawings, components similar to those described or illustrated in a drawing thereinabove are marked with like reference numerals, and a detailed description is omitted as appropriate.